Combined Temporal Partitioning and Scheduling for Recon gurable Architectures

Dynamically Reconngurable processors are becoming increasingly viable with the advent of modern eld-programmable devices. A key feature of dynamically reconngurable FPGAs is that the logic, and interconnect is time-multiplexed. This enables the implementation of large circuits by partitioning the speciication into multiple segments, that execute one after the other on the reconngurable processor. The available resources can be reused which gives us virtually an innnite pool of resources. In this paper, we introduce a novel technique of temporal partitioning and synthesis of behavioral speciication for reconngurable architectures. We try to optimize the overall latency by performing a trade-oo between the total number of partitioned segments, and the latency of each segment. Our approach integrates partitioning and scheduling, and performs design space exploration to exploit the trade-oo. We also introduce an enhanced Force-Directed List Scheduling (FDLS) algorithm to perform partitioning. We demonstrate the eeectiveness of our approach with experimental results.